A detailed introduction to flash storage devices and flash storage systems

On June 28th, the event initiated by the Shanghai Storage Specialized Committee was successfully held in Anhui University. Professor Shi Liang from East China Normal University gave a keynote speech entitled “Research on Parallel Optimization Technology of New Generation Flash Storage System” . Let’s take a look at the content of this online meeting with the editor.

On June 28th, the event initiated by the Shanghai Storage Specialized Committee was successfully held in Anhui University. Professor Shi Liang from East China Normal University gave a keynote speech entitled “Research on Parallel Optimization Technology of New Generation Flash Storage System” . Let’s take a look at the content of this online meeting with the editor.

Professor Shi Liang gave a detailed introduction to flash memory storage devices and flash memory storage systems, and shared the research group’s research on parallel technology. Finally, make a conclusion of this speech.

01
flash device

The internal structure of flash memory device includes chip, chip controller, storage processor, cache, controller memory and interface.The current mainstream interfaces include UFS, SATA, PCIe, etc.

A detailed introduction to flash storage devices and flash storage systems

A detailed introduction to flash storage devices and flash storage systems

Internal structure of flash memory

A detailed introduction to flash storage devices and flash storage systems

02

flash storage system

A detailed introduction to flash storage devices and flash storage systems

Questions to consider:

1. Are high-speed SSDs suitable for traditional database design?Solid State Storage Database Design

2. Can traditional file system designs manage SSDs efficiently? Solid State Storage File System (F2FS)

3. Can traditional schedulers take full advantage of SSDs? Solid state storage scheduler (multi-queue)

4. Is the traditional system architecture suitable for SSD?Solid State Storage System Storage Architecture

03

Parallel optimization design

Next, Prof. Shi Liang introduced the three tasks of the team’s research: 1) Parallel optimization design based on the minimization of flash memory access conflicts

2) Garbage collection based on chip idle time leads to access conflict optimization strategy

3) Performance optimization design based on maximizing parallelism of flash memory system

Parallel Optimal Design Based on Minimization of Flash Access Conflicts
Exploiting Parallelism in I/O Scheduling for Access Conflict Minimization in Flash-based Solid State Drives

Question: Introduce the serious low utilization of chips in flash memory, that is, the number of flash memory chips being accessed at the same time is not high, which is mainly caused by access conflicts between I/O requests.

Solution: Professor Shi Liang introduced the solution Parallel Issue Queue (PIQ) in a paper published by the team, which aims to minimize access conflicts between I/O requests through scheduling.

PIQ schedules non-conflicting I/O requests into the same batch and conflicting I/O requests into different batches. Therefore, by taking advantage of the parallelism of SSDs, multiple I/O requests in a batch can be satisfied simultaneously.

A detailed introduction to flash storage devices and flash storage systems

A detailed introduction to flash storage devices and flash storage systems

A detailed introduction to flash storage devices and flash storage systems

Garbage collection based on chip idle time leads to access violation optimization strategy

Exploiting Chip Idleness for Minimized Garbage Collection Induced Chip Access Conflict on Solid State Drives

Problem: Due to the non-in-place update feature of flash memory, garbage collection operations will be frequently performed internally to reclaim invalid pages, and when internal activities are frequently triggered, host I/O performance will be severely affected by access conflicts between them.

Solution: In order to improve the performance degradation caused by the access conflict caused by garbage collection, Professor Shi Liang introduced the solution in the paper and proposed a new access conflict minimization solution. Describes the use of the idle time of multiple chips of an SSD to schedule operations caused by internal activities to minimize access conflicts.

The method is implemented in two steps: first, the data accessed by the internal activity is read to the controller; second, the data accessed by the internal activity is written back to these idle chips by utilizing the idle chips during the internal activity.

A detailed introduction to flash storage devices and flash storage systems

A detailed introduction to flash storage devices and flash storage systems

A detailed introduction to flash storage devices and flash storage systems

Performance optimization design based on maximizing parallelism of flash memory system

Parallel all the time: Plane level parallelism exploration for high performance solid state drives

Problem: Flash memory consists of multiple levels of parallelism, including channel, chip, die and plane. Of these parallelism levels, plane-level parallelism has the most restrictive limits. Only operations of the same type accessing the same address in different planes can be processed in parallel. Plane-level parallelism is not yet well utilized and should be further improved.

Scheme: In this work, Professor Shi Liang introduces a parallel optimization method from plane to die to exploit plane-level parallelism by intelligently satisfying strict constraints.

A detailed introduction to flash storage devices and flash storage systems

A detailed introduction to flash storage devices and flash storage systems

A detailed introduction to flash storage devices and flash storage systems

The parallelism of flash memory is a very important topic, but how to fully exploit and make good use of the parallelism of flash memory is very important!

In this report, three aspects of flash parallelization technology are introduced:

1) From the system point of view, the parallel scheduling method is proposed to realize the utilization of the parallel capability of flash memory

2) From the perspective of the controller, it is proposed to parallelize the most expensive operation in the flash memory, GC

3) From an architectural point of view, it is proposed to design a deep parallel optimization technology by utilizing the deep parallel characteristics of flash memory

In the future, we will conduct a lot of research on the quality of service of flash memory, and use the parallel ability of flash memory to provide high-quality services!

The Links:   PM50RVA120 SCE200AA160

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