Munich, Germany, October 26, 2021 – Codasip, a leading supplier of semiconductor intellectual property (IP) cores for custom RISC-V processors, today announced further enhancements to its Studio processor design tool suite. New additions to its Studio 9.1 tools include full AXI bus support added for high-performance designs, improved support for LLVM, and higher code density.
Studio tools are a core component of the Codasip product portfolio and can be used to simplify custom design tasks, enabling companies of all sizes to differentiate their products from the core of the processor. Studio has been a leader in the emerging processor market since the tool suite launched in 2014. By simplifying the processor customization process, when designers use Codasip’s embedded processor or application processor core designs to customize their ideal RISC-V processor, Studio can help them automate the necessary steps to achieve the most optimal RISC-V processor. best performance.
Studio brings these values to the rapidly growing global RISC-V developer community, and with today’s release of the Studio 9.1 tool suite, will continue to expand the tool’s leadership in enabling high-performance and low-cost designs.
The special feature of version 9.1 tool suite is that Studio users can get richer bus interfaces, that is, after adding a complete AXI bus this time, it means that Studio has been able to support users to develop more powerful application processors and applications. multi-core system.
In the design of embedded processors, the size of the instruction memory can determine the cost, so the improved code density in Studio 9.1 will help reduce the overall cost of the system.
Codasip’s latest update includes an LLVM-based SDK with a fast C/C++ compiler and the Linker Support Package, both of which were added to the tool suite with the release of Studio 9.0 in April 2021 . In applications processors running more complex operating systems such as GNU/Linux, this upgrade can significantly improve support for custom instruction sets. Another new feature provides support for ISA subtargets, which greatly reduces the maintenance cost of multiple SDKs for different ISA configurations.
Zdenēk Prikryl, Chief Technology Officer of Codasip, said: “We have been continuously driving the evolution of our tool offerings, stemming from the diversity of customer types, so our new projects and developments are continuously designed for these Development tools bring advancements. Codasip is committed to simplifying designs for our differentiated processor cores and tools: they have all been built to easily bring value to customers of all sizes, enabling customers to combine high performance, A cost-effective, differentiated product is brought to market quickly and easily.”
Codasip provides leading RISC-V processor IP and advanced processor design tools, providing chip designers with all the advantages of the RISC-V open instruction set architecture (ISA), as well as the unique ability to customize processor IP. As a founding member of the RISC-V International Foundation and a long-term provider of LLVM and GNU-based processor solutions, Codasip is committed to advancing open standards for embedded processors and application processors. The company was founded in 2014 and is headquartered in Munich, Germany; Codasip currently has several R&D centers in Europe and branches in China, and its sales representatives cover the world.