CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection

This article compares the design complexity behind aliasing suppression solutions for existing precision ADC architectures. We will present a theory to account for the inherent aliasing rejection of the CTSD ADC architecture itself. We also show how to simplify signal chain design and discuss the scaling benefits of CTSD ADCs. Finally, we introduce new measurement and performance parameters to quantify aliasing suppression.

By Smita Choudhury and Abhilasha Kawle, Analog Devices

In Part 3 of the CTSD Precision ADC article series, we will focus on the alias-free nature of the CTSD ADC, which improves noise immunity without adding any peripheral design. Part 1 presents a new, easy-to-use, alias-free precision ADC based on a continuous-time sigma-delta DAC (CTSD) architecture that provides a simple, compact signal chain solution. Part 2 introduces CTSD technology to signal chain designers. This article compares the design complexity behind aliasing suppression solutions for existing precision ADC architectures. We will present a theory to account for the inherent aliasing rejection of the CTSD ADC architecture itself. We also show how to simplify signal chain design and discuss the scaling benefits of CTSD ADCs. Finally, we introduce new measurement and performance parameters to quantify aliasing suppression.

In many applications such as sonar arrays, accelerometers, vibration analysis, etc., signals outside the bandwidth of the signal of interest will be monitored and these signals are called interferers. A key challenge for the signal chain designer is that ADC sampling can cause these interferers to alias into the desired signal bandwidth (in-band), degrading performance. In addition to this, in applications such as sonar, in-band aliased interferers can be misinterpreted as input signals, leading to misjudgment of objects around the sonar. The aliasing mitigation solution is one of the reasons why traditional ADC signal chain designs are extremely complex. CTSD ADCs inherently have alias rejection, a unique feature that leads to a new simplified solution. Before discussing this breakthrough solution, let’s first understand the concept of aliasing.

Review the Nyquist Sampling Criterion

To understand the concept of aliasing, let’s quickly review the Nyquist sampling criterion. We can analyze signals in the time or frequency domain. In the time domain, the sampling of an analog signal can be mathematically represented as a signal multiplication operation, e.g. x

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection
Figure 1. Time-domain representation of the sampling process

Likewise, in the frequency domain, the sampled output can be represented by a Fourier series as:

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection

It can be seen from formula 1 that if the frequency axis is expanded, it will be at each sampling frequency fsThe integer multiples of the positions form the image of the input signal.

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection
Figure 2. Representation of X(f) after sampling at different sampling frequencies

Equation 1 shows that at frequency f = n × fs – fINwhere n = 0, ±1, ±2…, the signal content X(f) will appear at fIN after sampling, similar to the undersampling scenario in Figure 2, which shows the sampling under various conditions Phenomenon.

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection

In summary, the Nyquist criterion states that any signal greater than half the sampling frequency will be folded or reflected back below fs/2 and may fall within the target band.

Suppose the ADC is at frequency fsdownsampling, while there are two out-of-band tones/interference sources in the system, f at the ADC input1and f2,As shown in Figure 3. According to the Nyquist criterion, we can infer that due to the signal tone f1frequency less than fs/2, so its frequency remains the same after sampling. When the signal tone f2frequency greater than fs/2, it will be in the target frequency band fbw_inAliasing occurs in this region and degrades the ADC performance in this region, as shown in Figure 3a.

This theory also applies to fsNoise above /2, which can also fold and appear in-band, increases the in-band noise floor and degrades performance.

Existing aliasing suppression solutions

To avoid this performance degradation caused by out-of-band (OOB) tones or noise folding, a simple solution is to use a low-pass filter to filter over f before sampling by the ADC.sThe signal content of /2 is attenuated, and the filter is called an anti-aliasing filter (AAF). Figure 3b shows the transfer function of a simple AAF, along with the frequency f2Attenuation at – the state of the aliased tones before they are folded in-band. The main characteristic parameters of this AAF are the filter order and the C3 dB corner frequency. They are determined by the passband flatness, the absolute attenuation required at a particular frequency (such as the sampling frequency), and the slope of the attenuation required outside the input bandwidth (also known as the transition band). Some common filter architectures include Butterworth, Chebyshev, Bessel, and Sallen-Key, which can be implemented using passive RCs and op amps. Filter design tools are available to assist the signal chain designer with the AAF design for a given architecture and requirements.

Let us understand the requirements of an anti-aliasing filter with an application example. In submarine systems, sonar sensors emit sound waves and analyze underwater echoes to estimate the location and distance of surrounding objects. The input bandwidth of this sensor is 100 kHz, and the system uses a signal tone with an amplitude > C85 dB detected at the ADC input as an effective echo source. Therefore, any interference from out-of-band needs to be attenuated by at least C85 dB by the ADC to avoid being detected as input by the sonar system. In the next section, we will build and compare alias mitigation solutions for different ADC architectures for these requirements.

In traditional ADC architectures, such as successive approximation register (SAR) and discrete-time sigma-delta (DTSD) ADCs, the sampling circuit is located at the analog input of the ADC, indicating the need to use the AAF before the ADC input, as shown in Figure 3b.

AAF Requirements for SAR/Nyquist Sampling ADCs

The sampling frequency of the SAR ADC is generally set to the analog input frequency (fIN) twice or four times. The AAF of this ADC needs to be at frequency fINThere is a narrow transition band outside, which means a higher order filter is required. As can be seen from Figure 4, a SAR ADC with a sampling frequency of about 1 MHz requires a fifth-order Butterworth filter to achieve C85 dB rejection at frequencies greater than 100 kHz. For filter implementations, as the filter order increases, so does the number of passive and op amps required. This means that AAF for SAR ADCs requires a large power and area budget in the signal chain design.

AAF Requirements for DTSD ADCs

Sigma-delta ADCs are oversampling ADCs, where the sampling frequency is much higher than the analog input frequency. The aliasing region to be considered in AAF design is fs ± fIN. The transition band of the filter is required from fINto very high fs. Compared with the SAR ADC AAF, this transition band is wider, which means that the required AAF order is also lower. As can be seen from Figure 4, for a DTSD ADC with a sampling frequency of 6 MHz, ifs C85 dB aliasing suppression at frequencies around C 100 kHz typically requires the use of a second-order AAF.

In practical applications, interference or noise may exist anywhere within the frequency band, not limited to the sampling frequency fsnearby. any lower than fs/2 frequency signal tone (frequency f in Figure 31tones below) will not appear in-band, thereby not degrading ADC performance. Although AAF can1There is some attenuation, but it will still be present in the ADC output as excess information that the external digital controller must process. Can this tone be attenuated further so that it no longer appears in the ADC output? One solution is to use at frequency fINAAF with narrow transition band outside, but this will increase the complexity of filter design. Another solution is to use an on-chip digital filter in the sigma-delta modulator loop.

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection
Figure 4. AAF complexity, ADC architecture, and target frequency band

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection
Figure 5. STF of a DTSD ADC with AAF on the front end and digital filter on the back end.

Digital Filter for Sigma-Delta Modulator Loop

In sigma-delta ADCs, due to oversampling and noise shaping, there is a lot of redundant information in the modulator output, which requires extensive processing by an external digital controller. If the modulator data is averaged, filtered, and processed at a lower output data rate (ODR) (typically 2 × fIN), you can avoid this redundant information processing. Using a decimation filter, the sampling rate can be changed from fsConvert to the desired lower ODR. Regarding the use of digital filters for sample rate conversion, which we will cover in a future article, the key point here is that discrete-time sigma-delta modulators are often used in conjunction with on-chip digital filters. The combined signal-to-interference transfer function (TF) of the modulator with an analog filter at the front end and a digital filter at the back end is shown in Figure 5.

In summary, the AAF of a DTSD ADC is based on the aliasing region fsdesigned for the desired attenuation of surrounding tones. non-aliasing regions (e.g. f1) are completely attenuated by the on-chip digital filter.

Back-end digital filters and front-end analog filters

SAR ADCs require narrow transition bands for AAFs, while sigma-delta ADCs require narrow transition bands for digital filters. The digital filter has low power consumption and is easy to integrate on-chip. Also, programming the order, bandwidth, and transition band of a digital filter is much simpler than an analog filter.

The advantage of oversampling is that it allows a combination of wide-transition-band analog filters and narrow-transition-band digital filters in the back end to provide a solution with superior power consumption, size, and noise immunity.

With DTSD ADCs, the AAF requirements are relaxed, but the design complexity is increased to meet the settling time requirements after each sample, thereby avoiding signal chain performance degradation. The challenge for the signal chain designer is to fine-tune the AAF to find a balance between the need for aliasing suppression and the need for output stability.

The new precision CTSD ADC simplifies signal chain design by eliminating the need for front-end analog filter design.

Inherent aliasing rejection of CTSD ADCs

Part 2 of this article series presents a first-order CTSD modulator constructed from a closed-loop resistive inverting amplifier, as shown in Figure 6. CTSD modulators follow the same oversampling and noise shaping concepts as their DTSD modulator equivalents to achieve expected performance, and have resistive inputs instead of switched capacitor inputs. The modulator building block consists of a continuous-time integrator followed by a quantizer to sample and digitize the integrator output, and a feedback DAC to close the input loop. Any noise at the input of the quantizer is noise shaped by the gain transfer function of the integrator.

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection
Figure 6. (a) Building blocks of the CTSD modulator loop and (b) simplified block diagram for mathematical analysis.

Based on the information in Part 2, a simplified block diagram of the CTSD modulator loop can be drawn using the following mathematical model:

The integrator transfer function is commonly referred to as H(f), also known as the loop filter. For a first-order integrator, H(f) = 1/2πRC.

The function of the ADC is sampling and quantization. Therefore, the simplified ADC model for analysis uses a sampler followed by an additive quantization noise source.

A DAC is a block that multiplies an input by a constant during the current clock cycle. So, it is a block with a constant impulse response during the sampling clock period and a zero impulse response the rest of the time.

Equivalent block diagrams of these simplified models are shown in Fig. 6b and can be widely used for ∑-∆ performance analysis. from VINto VOUTThe transfer function of is called signal TF (STF), from QeThe function to the output is called Noise TF (NTF).

A plausible explanation for the inherent aliasing suppression of the CTSD modulator loop is that the sampling does not take place directly at the input of the modulator, but after the loop filter H(f), as shown in Figure 6a. To understand the big picture, a linear model without a sampler will be used to understand the concept and the analysis will be expanded to cover loops with samplers.

Step 1: Implement STF and NTF analysis using linear models

After ignoring the sampler to simplify the analysis, the linear mode should look like Figure 7.The STF and NTF of this loop can be expressed as

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection

According to Equation 3, STF can be rewritten as

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection

The target frequency bandwidth is low frequency, which can be expressed mathematically as f→0, and high frequency can be expressed as f→∞. The magnitude (unit: dB) of STF and NTF is a function of frequency, as shown in Figure 7.

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection
Figure 7. (a) Linear model for simplified analysis, (b) STF(f) = H(f) × NTF(f)

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection
Figure 8. (a) Block diagram of a CTSD modulator loop, input = 0 V, (b) NTF of the modulator loop

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection
Figure 9. Relayout of the modulator loop to show its inherent aliasing rejection

NTF is similar to a high-pass filter, and STF is similar to a low-pass filter, with a flat 0 dB amplitude in the frequency band of interest, and attenuation at high frequencies comparable to an AAF TF. Mathematically, the signal is passed through a low-pass filter with high gain configuring H(f) and then processed by the NTF loop. Now, after understanding the NTF block diagram, it is possible to take a closer look at the loop with the sampler.

Step 2: Block Diagram of NTF

When the input VINWhen set to 0 V, the modulator loop block diagram can be rearranged as shown in Figure 8a to represent the NTF. When a sampler is included in the loop, the NTF response is similar to the linear model, but at fsThe duplicated images are displayed at multiple positions of , as shown in Figure 8b.

Step 3: Rearrange the modulator loop to visualize the prefilter operation

If the loop filter H(f) and the sampler of the modulator loop are moved to the input, and the feedback is shown in Figure 9, the input-to-output transfer function does not change. The right side of the rearranged block diagram represents NTF.

Similar to the linear model in step 1, in a sampled equivalent system, the input signal is passed through a high gain H(f) and then sampled and processed through an NTF loop. The transverse portion of the signal after passing through the loop filter forms a low-pass filter configuration before sampling. This configuration results in the inherent aliasing rejection of CTSD modulators. Therefore, the STF of the CTSD modulator loop is shown in Figure 9.

Step 4: Complete the STF with a digital filter

To reduce redundant high-frequency information, a CTSD modulator is used in conjunction with an on-chip digital decimation filter, and the combined aliasing suppression TF is shown in Figure 10. fsNearby aliasing is attenuated by the inherent aliasing suppression properties of CTSD, and intermediate sources of interference are attenuated by digital filters.

Figure 4 compares the number of AAF orders required to achieve C80 dB of aliasing rejection for SAR ADCs, DTSD ADCs, and CTSD ADCs at sampling frequency and input signal bandwidth. When using a SAR ADC, the AFF has the highest order and therefore the highest complexity, while a CTSD ADC does not require an external AAF due to the inherent aliasing rejection of the design.

Leveraging CTSD Architecture to Achieve the Advantages of Signal Chains

In some multi-channel applications such as sonar beamforming and vibration analysis, phase information between channels is very important. For example, the phase between channels needs to be precisely matched to an accuracy of 0.05° at 20 kHz.

For traditional ADC signal chains, passive RCs and op amps are used in the AAF design. The filter causes a certain magnitude and phase drop in band as a function of the corner frequency. In order to achieve good channel-to-channel phase matching, all channels need to have the same dip, indicating the need for fine control and matching of the filter corner frequencies for each channel. Designed for use at 16 MHz (sampling frequency) as well as 160 kHz f3dBA second-order Butterworth filter that achieves C80 dB rejection at 20 kHz may have a phase mismatch of ±0.15° at 20 kHz, and the error tolerance may be as low as 1% of the absolute value of RC. Available smaller error tolerant RC passives are limited and increase the bill of materials (BOM).

Since AAF is not required in the CTSD ADC signal chain, channel-to-channel amplitude and phase matching is naturally achieved within the frequency band of interest. The phase mismatch is limited by the on-chip mismatch of the analog modulator loop design and can be as low as ±0.02° at 20 kHz.

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection
Figure 10. CTSD Modulator Loop with Back-End Digital Filter

Measure and quantify inherent aliasing suppression

The data sheet of the AD4134, a precision ADC based on the CTSD ADC architecture, describes a new feature check for measuring aliasing rejection. The analog input signal frequency to the ADC is swept and the effect of each out-of-band input signal is calculated by measuring the folded amplitude (if any) of the test frequency tones relative to the used tones.

Figure 11 shows the AD4134’s alias rejection performance for out-of-band frequencies with a performance bandwidth of 160 kHz and a sampling frequency of 24 MHz. For 23.84 MHz (fs C 160 kHz) frequency, the alias rejection is C85 dB, which is the ADC’s alias rejection specification. It can also be seen from the figure that for other intermediate frequencies, the aliasing rejection is higher than C100 dB. See the AD4134 data sheet for more details on inherent aliasing rejection, and options to further improve this rejection.

CTSD Precision ADCs – Part 3: Implementing Intrinsic Aliasing Rejection
Figure 11. Aliasing Rejection vs Out-of-Band Frequency

The CTSD ADC concepts we describe in this article help signal chain designers understand the resistive input, resistive reference, and inherent aliasing rejection characteristics of this architecture. An easy-to-drive input and reference, and no AAF design in the CTSD ADC signal chain, combine to create a new simplified ADC front-end design suitable for a variety of applications. Read the next installment in this series to learn more about these simplified precision signal chain designs!

The Links:   2SB1132T100Q 2DI200A-050P

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