Design of Airborne Embedded Computer System Based on PCI Bus Chip PCI9056

The PCI bus originated from microcomputers and has become the de facto bus standard for microcomputers. Because of its many functions, strong compatibility and leading the way. Devices designed for the PCI local bus are PCI-specific rather than CPU-specific, independent of processor upgrades. The goal is to implement systems with as little current as possible, with low power consumption.

Author: Jiang Yunsheng

The PCI bus originated from microcomputers and has become the de facto bus standard for microcomputers. Because of its many functions, strong compatibility and leading the way. Devices designed for the PCI local bus are PCI-specific rather than CPU-specific, independent of processor upgrades. The goal is to implement systems with as little current as possible, with low power consumption. Software is transparent. When communicating with PCI devices, the same command set and state definitions are used between software drivers. With the development of embedded computers, the PCI bus has been introduced into embedded systems more and more. This article introduces some experiences and experiences of implementing embedded PCI bus in the “Tenth Five-Year Plan” pre-research project, and discuss with you.

1 PCI bus overview

PCI (Peripheral Component Interconnect) bus, that is, the peripheral component interconnect bus. In the PCI application system, if a device has obtained the bus control, it is called “master”, and the device selected by the master to communicate is called “slave”.

The system signals include a reset signal RST and a clock signal CLK. Arbitration signals include bus request REQ and bus grant signal GNT. The interface control signals include the FRAME signal that the master device initiates the PCI transaction, the transaction data valid signal IRDY of the master device, and the signal TRDY that the target completes this data transaction. PCI does not have read and write signals for general data cycles, but uses command coding to define the read and write attributes of this PCI cycle. Each PCI cycle is initiated by the master device. In the first clock cycle, the AD[31..0]signal carries the address information, and the combination of C/BE[3..0]represents the command and defines the PCI cycle. The second clock hand, AD[31..0]is driven by the party providing the data, and the combination of C/BE[3..0]represents a valid byte. Details can be found in the bibliography, namely the PCI specification.

Design of Airborne Embedded Computer System Based on PCI Bus Chip PCI9056

2 PCI bus design

At present, there are many manufacturers and chips that can support the PCI bus. Among them, the PCI9056 of American PLX Company has the most complete functions and is easy to use. The following design uses the PCI9056 as the main model.

2.1 PCI system clock

The signal driving of the PIC bus adopts the reflected wave method instead of the traditional incident wave. In this way, the deviation of the sampling time of each device is very high, that is, the skew (skew) of the clock should be as small as possible, and the maximum clock skew is ≤2ns. It is best to use the same time for each device in the entire PCI system; however, the driving capability of the same clock is limited, and it is impossible to drive all PCI devices synchronously. The IDT74CT3807 clock driver can solve this problem. It converts one clock source into 10 equivalent clocks with a skew between the clocks ≤350ps. Figure 2 is a PCI clocking solution.

Design of Airborne Embedded Computer System Based on PCI Bus Chip PCI9056

Obviously, excluding central resources, this PCI system can bring up to 9 devices, which is enough for embedded systems. On the PCI backplane, in order to ensure the skew rate of the clock, each PCI clock must go on an equal-length line.

2.2 Central resources and PCI adapters

In the PCI system bus, there must be a PCI host bridge (Host) to manage the entire bus. The host bridge provides system signals and performs indecision arbitration in the PCI department. PCI9056 can work in Host mode or as a common PCI adapter. Figure 3 is the principle of two working modes.

Design of Airborne Embedded Computer System Based on PCI Bus Chip PCI9056

When the HOSTEN pin is connected to the ground, the PCI9056 works in the Host mode, that is, it becomes the central resource of the system. In the Host mode, the local reset LRESET of the PCI9056 is an input, which receives the reset from the local CPU, etc., and then generates a PCI bus reset in the RST. , to reset other devices on the entire PCI bus. The PCI9056 working in the adapter mode is just the opposite. RST receives the reset from the PCI bus, and then resets other devices in the PCI device through LRESET. Generally, the PCI8056 of the main bridge is set as the bus arbiter. Note that the two arbitration signals REQ and GNT are connected interchangeably.

When PCI9056 is used as an adapter, REQ and GNT are used for arbitration signals. When it acts as a bus arbiter, there are other pairs of request-response signals that can be used. Not shown in FIG. 3 .

2.3 Power-on initialization

If PCI9056 is designed as the main bridge (North Bridge) of the system, that is, the central resource (Host), there is a CPU on its local bus side. The initialization of the register can be carried out by the CPU, or it can be automatically loaded by the internal parameters stored in the EEPROM. If the PCI9056 is used as an adapter of a general PCI device and generally does not have a CPU, the internal register can be set by the initialized host bridge through the PCI configuration cycle, or it can be automatically loaded by the EEPROM during power-on. The EEPROM in Figure 4 can be either FM93C56 or FM93CS56 from Fairchild. All internal registers can be set by the local CPU, and the control logic should generate the CCS chip select. If the EEPROM is not used to automatically load the initialization parameters after power-on, a 1kΩ resistor should be pulled down on the DI/DO pin. In addition to local CPU initialization and EEPROM power-on automatic initialization, more PCI devices are dynamically initialized by the host bridge through the PCI bus. The system software should ensure that the PCI space of each device does not overlap.

Design of Airborne Embedded Computer System Based on PCI Bus Chip PCI9056

3 Software Design

The PCI bus is not easy to debug, not only because the hardware design is complicated, but also because the driving software is quite difficult. But as long as a few basic concepts and functions are subtly embodied in the software, the entire driver software will be very clear. The following codes are some mature driver functions in the TMS320C6701 environment.

3.1 Configure the host bridge as the master device of the PCI bus

When initializing other devices of the PCI bus, the central resource acts as the master device of the PCI bus. At this time, all registers are set by the local CPU, and the task PCI cycle is not generated, that is, the local logic must decode and generate the CCS signal.

//Function: Parameters when configuring the PCI9056 of the central resource as the master device
// entry parameters
//Range: image range length
//PCIBAddr: PCI base address
//LocBAM: local memory base address
//LocBAMI: Local I/O configuration base address
void ConfigHostMaster(UINT Range, UINT PCIBAdr, UINT LocBAM, UINT LocBAMI)
{UINT Aword;
//PCI command code register CNTRL
//D3..0=PCI Read Command Code for DMA
// Default 1110b:Memory Line Read, memory line read
//D7..4=PCI Write Command Code for DMA
// Default 0111b:MemoryWrite, memory write
//D11..8=PCI MemoryRead Command Code for Direct Master,
// default 0110b:MemoryRead memory read
//D15..12=PCI MemoryWrite Command Code for Direct Master.
// Default 1110b:MemoryWrite, memory write
//D30=1: reset the PCI side
//Just use this default value, which is 000F.767EH
*(int*)LOC_CNTRL=*(int*)LOC_CNTRL|0x400000000;
Aword=0x000FFFFF;
While(Aword–); //Reset lasts
*(int*)LOC_CNTRL=*(int*)LOC_CNTRL & 0xBFFFFFFF;
//Clear software reset
//PCI Arbitration Controller PCIARB
*(int *)LOC_PCIARB=0x00000001;//The central resource should be the PCI bus arbiter
//—Direct Master-to-PCI Address Mapping—
//Local base address+Range->PCI address mapping. –
//Local base address+Range->PCI base address+Range
//1. Range register DMRR
//Length range value DMRR
//The length range value should be a multiple of 64KB, that is, D15..0=0000H
//And the filled value should be the code of the length value, that is, change +1, such as
//64KB=0001.0000H–>FFFE.FFFFH+1=FFFF.0000H
//1MB=0010.0000H–>FFEF.FFFFH+1=FFF0.0000H
*(int *)LOC_DMRR=(~Range)+1;//Image range
//2. Local memory base address DMLBAM (P11-29)
//D15..0:Reserved.
//D31..16: The high 16 bits of the base address must be a multiple of the range value
*(int *)LOC_DMLBAM=LocBAM;
//3. Local I/O Configuration base address DMLBAI
//When configuration access is enabled, accessing the base address pointed to by this register will generate a PCI configuration cycle
*(int *)LOC_DMLBAI=LocBAMI;
//4.PCI base address register DMPBAM(P11-30)*(int*)LOC_DMPBAM=PCIBAddr|0xE3;
*(int *)LOC_DMCFGA=0x00000000;//The configuration cycle is not generated temporarily
*(int*)LOC_DMDAC=0x0; //The high 32-bit address is always 0, need double address
//5. Command register PCICR (P11-8)
//D0=IO Space=”1: To respond to the I/O cycle”.
//D2=Master Enable=”1: Allow to be Master”.
*(int *)PCI9056_PCICR|=0x00000007;
return;
}

When other devices on the PCI bus need to access the central resource, the master bridge becomes a slave device, so the parameters of its PCI space to local space mapping should be configured. This process is an inverse transform, and the code is omitted here.

3.2 Configure PCI bus slave device

When a central resource accesses other PCI devices as a master, the slave must be properly initialized. Generally, the PCI configuration cycle is used to set the key configuration registers of the PCI bridge, and then the other registers are set with the ordinary PCI memory cycle.

Void ConfigPCISlave(UINT And, UINT Range, UINT PCIBAdr, UINT LRegPBA, UINT LocBAdr)
//Function: Generate a PCI configuration cycle through the main bridge to configure the PCI9056 as a slave on the PCI bus
//Entry parameters:
//ADn: device number, that is, the PCI address connected to the IDSEL# of the configured device
//Range: Range length
//PCIBAddr:PCI base address
//LRegPBA: PCI memory base address of internal registers (range 512B),
//That is, the PCIBAR0 value
//LocBAddr: local base address
{UINT Abit32W, LROffset;
//——Use the configuration cycle——————–
//Set the command register PCICR
//D0=IO Space=”1: To respond to I/O cycles”
//D1=Memory Space=”1: To respond to the Memory cycle”
//D2=Master Enable=”1: Allow to be Master”
ABit32W=GetConfigReg(ADn, PCI9056_PCICR)|0x07;
//read the original value and set it
SetConfigReg(and, PCI9056_PCICR, ABit32W);
//PCIBAR0: PCI base address of other registers.
SetConfigReg(ADn, PCI9056_PCIBAR0, LRegPBA);
//Set the PCI base address so that other registers can be accessed
SetConfigReg(ADn, PCI9056_PCIBAR2, PCIBAddr);
//——- The following uses PCI memory cycles ——–
//1.Space0’s local address range LAS0RR
LROffset=LRegPBA&0x001FFFFF;//Get the displacement of the PCI base address of the local register
ABit32W=~Range+1; //Calculate the complement of the range value
SetPCIReg(LROffset, PCI_LAS0RR, Abit32W);
//2.Space0’s local base address LAS0BA
SetPCIReg(LROffset, PCI_LAS0BA, LocBAddr|1);
SetPCIReg(LROffset, PCI_EROMBA, 0x38);
//4.Space 0/ROM’s local bus descriptor LBRD0 (P11-27)
//D1D0=11:Space 0-32Bit data width. (reset default)
//D5..2=Internal wait state counter.
//D6=1: READY# signal is required. (reset default)
//D7=1: allow continuous Burst
//D7=0:Burst-4 Mode (reset default)
//D8=0: Space 0 allows prefetching
//D9=0: Extended ROM allows prefetching
//Use the default value 40430043H
SetPCIReg(LROffset, PCI_LBRD0, 0x40430043);
ABit32W=GetPCIReg(LROffset, PCI_LBRD0);
if(ABit32W!=0x40430043)
printf(“Error in default value of local bus descriptor LBRD0=%8x”, ABit32W);
return;
}

The identities of other devices on the PCI bus change dynamically, so for those capable of being a PCI master device, the parameters for mapping their local space to PCI space should be configured.

Epilogue

The PCI local bus specification is also being updated, moving in the direction of being faster, stronger and more power efficient. The clock rate is increased from the initial 33MHz to 66MHz, the data width is also extended from 32 bits to 64 bits, and the operating voltage is changed from 5V to 3.3V, making the power consumption smaller. It can be expected that the embedded PCI bus will greatly improve the overall performance of the airborne embedded computer system.

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