The working principle and function realization design of automatic mode change control PLL

At present, digital phase-locked loop has been widely used in digital communication, radar, radio electronics, instrumentation, high-speed computer and navigation system. Compared with the traditional analog phase-locked loop, the all-digital phase-locked loop overcomes the shortcomings of the analog phase-locked loop that is susceptible to voltage changes and temperature drift, so it has the advantages of stable operation, high reliability, and easy implementation.With the development of large-scale programmable logic devices, it not only brings unprecedented convenience to the design of all-digital phase-locked loops, but also can use the entire system as a functional module to be embedded in SoC (SysteIn on Chip) to form an on-chip lock. phase loop, improving the efficiency of the loop

At present, digital phase-locked loop has been widely used in digital communication, radar, radio electronics, instrumentation, high-speed computer and navigation system. Compared with the traditional analog phase-locked loop, the all-digital phase-locked loop overcomes the shortcomings of the analog phase-locked loop that is susceptible to voltage changes and temperature drift, so it has the advantages of stable operation, high reliability, and easy implementation. With the development of large-scale programmable logic devices, it not only brings unprecedented convenience to the design of all-digital phase-locked loops, but also can use the entire system as a functional module to be embedded in SoC (SysteIn on Chip) to form an on-chip lock. Phase loop, improve the working performance of the loop, which will be of great significance. There are various structural forms of the all-digital phase-locked loop, but they are all designed to achieve a faster phase-locking speed, a larger phase-locking range, and a smaller phase jitter. Most of the current all-digital phase-locked loops are based on the premise that the input signal frequency is known, and the clock frequency of the system is considered, and then the N value of the divide-by-N counter is determined. The center frequency of this type of all-digital phase-locked loop cannot be changed, so the frequency-locking range is limited. When the frequency of the input signal changes greatly, the phase-locked loop will not be able to reach the locked state. The literature designs a fast all-digital phase-locked loop with high-precision automatic variable mode control. This method can not only greatly improve the locking speed, but also greatly reduce the interference of noise to the loop. However, the frequency bandwidth of the digital phase-locked loop is relatively small. narrow and limited in application. There are literatures on how to widen the frequency band of the digital phase-locked loop, and the main idea is to change the center frequency of the loop. The literature adopts the simple method of controllable analog/digital frequency divider to realize the all-digital phase-locked loop with small capture time and wide capture bandwidth, which solves the conflicting problem of “capture time” and “capture bandwidth”. However, the all-digital phase-locked loop realized by this method will not be able to lock when the frequency of the input signal changes abruptly.

A broadband all-digital phase-locked loop with automatic variable mode control is proposed here. On the basis of the traditional fully digital phase-locked loop with automatic mode change control, a unique frequency discrimination latch module is added, which can track the change of the input signal frequency at any time, and quickly realize the phase locking on the basis of locking the input signal frequency first. . The whole system is designed and implemented by VHDL language, and the system is simulated and verified by Quartus Ⅱ software, and the simulation results of the computer are given.

1 Structure and working principle of the all-digital phase-locked loop with improved automatic mode change control

Figure 1 shows the system block diagram of the improved automatic variable mode control full digital phase-locked loop. The phase detector in the figure adopts an edge-triggered phase detector, which has a larger phase detection range than the XOR gate phase detector. The linear phase detection range of the edge-triggered phase detector is ±π. The digital loop filter in this design is a variable-modulus K-reversible counter. The output ue of the phase detector is used as the count direction control signal of the K-reversible counter. When the count value of the K counter increases to K, the “add” command is output. ; On the contrary, when the count value of the K counter is reduced to 0, the “minus” command is output. In the working process of the system, the automatic variable mode controller counts the phase difference between the input signal ui and the output signal uo through the detection circuit, and then selects the appropriate modulo value mo through the comparison circuit and the analog-to-digital control circuit, and continuously updates the K counter. K value. As part of the numerically controlled oscillator, the pulse addition and subtraction circuit is the most important module in the whole system. The function of the pulse addition and subtraction circuit is to accurately insert and subtract a pulse in the local high-speed clock clk when receiving the “add” and “deduction” instructions, and use the adjusted pulse sequence as the clock source of the divide-by-N counter. The phase of the output signal uo is adjusted. The biggest feature of this design is that the N value of the N-counter module can be continuously updated according to the change of the input signal, so that the output signal uo can quickly track the frequency of the input signal ui, and at the same time, the center frequency of the system can be continuously updated to achieve broadband fast phase locking. the goal of. The detection of the N value is realized by the frequency discrimination and latch module. When the input signal ui is a rising edge, the internal counter starts to count, and the counter stops counting when ui becomes a low level. At the same time, when ui is low level, the counting result is sent into the latch as the frequency division value of the divide-by-N counter. The above is the working principle of the all-digital phase-locked loop of the improved automatic mode change control.

The working principle and function realization design of automatic mode change control PLL

From the above analysis, it can be seen that the designed all-digital phase-locked loop has two significant advantages: first, due to the use of the digital loop filter with automatic mode change control, the capture time and anti-noise performance of the loop are well resolved. contradiction between. The magnitude of the modulus value K has a great influence on the performance of the entire system. The larger the K value, the slower the system response and the longer the capture time; on the contrary, the smaller the K value, the faster the system response and the shorter the capture time. However, after the system enters the synchronization process from capture, if the K value is too small, continuous carry or borrow pulses will be generated due to the frequent cyclic counting of the reversible counter, resulting in the phase jitter of the output signal and increasing the synchronization error. After the automatic mode change control is adopted, the system can select and update the mode value K according to the magnitude of the phase error of the input/output signal. In the loop capture process, selecting a smaller modulus value can increase the loop bandwidth and speed up the locking speed; in the synchronization process, selecting a larger modulus value can reduce the loop bandwidth, which is beneficial to suppress phase jitter and reduce synchronization error, so that fast and high-precision phase locking can be achieved. Second, on the basis of the traditional all-digital phase-locked loop structure, a unique frequency discrimination latch module is added, which can not only capture and lock the unknown input signal, but also make the system have a wider frequency bandwidth and realize the change of frequency. fast locking of the input signal. The band widening principle of this design can be described as follows: in the frequency discrimination latch module, the calculation of the input signal frequency is based on the external high-speed clock as the clock source, and the higher the external clock frequency, the more accurate the N value obtained. The frequency values ​​that can be accurately calculated are equivalent to the center frequencies of different systems, and the phase-locked loop system has a capture band around each center frequency. Therefore, selecting a suitable external high-speed clock and different capture bands obtained by different center frequencies can constitute the capture band of the entire loop. Therefore, the design has a wider frequency band than the traditional digital phase-locked loop system. Figure 2 is a schematic diagram of the principle of frequency band broadening.

The working principle and function realization design of automatic mode change control PLL

2 System design and computer simulation results

The design is based on the Quartus II 7.1 development software platform produced by Altera, using the top-down system design method. First, according to the requirements of each functional module of the system, use VHDL language to write programs, and design the logic circuits of each part of the loop. And carry out simulation verification. Then, the parts are combined for system design and simulation. Finally, it is realized with FP-GA chip. Due to space limitations, here only the VHDL design and simulation of the frequency discrimination latch module are given as a list. The rest of the modules will not be described again. The VHDL source code for the top-level part of this module is as follows:

The working principle and function realization design of automatic mode change control PLL

The working principle and function realization design of automatic mode change control PLL

Figure 3 is the RTL schematic diagram of the frequency discrimination latch module synthesized by Quartus II 7.1. In the figure, JPQ and SCQ are the frequency discriminator and latch synthesized by the underlying VHDL code respectively, which realizes the function of frequency discriminating and latching the input signal. Figure 4 is a timing simulation waveform diagram of Quartus II 7.1. In Fig. 3, clk_up=1 ns is the clock source of the frequency discrimination latch module, fin is the input end of the input signal ui of the system, reset is the reset signal of the system, N[31. . 0]is the frequency discrimination result output by the latch. The simulation results show that the module can correctly complete the functions of frequency discrimination and latching.

The working principle and function realization design of automatic mode change control PLL

After the design simulation of each part in the loop is completed, the whole system is designed and verified. In the simulation diagram, clk is the system clock; reset is the reset signal; en is the system enable signal; fin and fout are input and output signals respectively; ue indicates whether fin is ahead or behind fout; add1, sub1 are “plus”, “deduction” Pulse signal; K is the quantized value of the phase error between fin and fout; N_mode is the N value of the divide-by-N counter. The automatic mode change control circuit divides the working process of the loop into: fast capture area, slow capture area and synchronization area according to the size of the error between the input and output signals. Figure 5 is the simulation waveform diagram of the input signal period Tui=23 ns. Figure 6 is the simulation waveform diagram of the input signal period Tui=100 ns.

The working principle and function realization design of automatic mode change control PLL

Figures 5 and 6 show that the design has fast tracking performance for both incoming high frequency and low frequency signals. Fig. 7 is the simulation waveform diagram that the input signal period Tui changes from 23 ns to 100 ns. Fig. 8 is the simulation waveform diagram that the period Tui of the input signal changes from 90 ns to 20 ns. Figures 7 and 8 show that the design has fast tracking performance for input signals with abrupt frequency changes (high frequency to low frequency and low frequency to high frequency).

The working principle and function realization design of automatic mode change control PLL

3 Conclusion

It can be seen through computer simulation that the designed all-digital phase-locked loop has a very fast phase-locking speed, and a large number of experiments show that the loop enters the locked state within 7 input signal cycles. It can be seen from the simulation results of Fig. 5 and Fig. 6 that the designed all-digital phase-locked loop has a wide frequency-locking range. In addition, the phase-locking accuracy has a lot to do with the external high-frequency clock of the system. If the clock frequency is high, the phase-locking accuracy will be higher. At the same time, the external high-frequency clock has a great relationship with the bandwidth of the all-digital phase-locked loop. In the frequency discrimination latch module, the frequency-divided clock of the external high-speed clock is used as the clock source. If the value is high, the frequency division value N obtained by frequency discrimination will be more accurate. In a word, the designed all-digital phase-locked loop with automatic mode change not only has a faster phase-locking speed, but also has a wider frequency-locking range and higher phase-locking accuracy when the external clock frequency is high.

The designed all-digital phase-locked loop has a simple structure and is easy to integrate. The VHDL language can be used to complete the system design, and it is convenient to use EDA software for comprehensive simulation. It can be made into an on-chip phase-locked loop. The next step is to focus on: study how to apply the ring numerically controlled oscillator, and use the control word to control the output of the ring numerically controlled oscillator to replace the external high-speed clock source in this design; The technique of using fractional frequency division improves the accuracy of the system.

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